Job Description

Job Title: VLSI Physical Design Engineer

Domain: VLSI / Semiconductor

Experience: 6 9 Years

Location: Anywhere in the USA / Remote

Notice Period: Immediate to 15 Days

Employment Type: Contract / Full-Time (as applicable)

Job Summary

We are seeking an experienced VLSI Physical Design Engineer with 6 9 years of hands-on experience in RTL-to-GDSII implementation, physical design optimization, and signoff closure. The ideal candidate will have strong expertise in Synopsys Fusion Compiler, timing closure, physical verification, and advanced semiconductor technology nodes such as 5nm and 3nm.

Key Responsibilities 1. RTL-to-GDSII Implementation

• Perform RTL-to-GDSII implementation using Synopsys Fusion Compiler.
• Execute synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and physical design optimization.
• Perform block-level and SoC-level floorplanning.
• Optimize design for timing, power, area (PPA), signal integrity, and design-rule compliance.
• Develop and maintain physical design constraints and implementation flows.

2. Timing Analysis and Signoff

• Perform static timing analysis (STA) and timing closure using Synopsys PrimeTime.
• Analyze setup and hold violations and implement corrective actions.
• Perform parasitic extraction and analysis using Synopsys StarRC.
• Drive timing closure across implementation and signoff stages.

3. Physical Verification and Reliability

• Perform physical verification, including Design Rule Checking (DRC), Layout Versus Schematic (LVS), antenna checks, and density checks using Siemens Calibre.
• Perform electromigration (EM) and IR-drop analysis and closure using RedHawk-SC.
• Ensure design compliance with foundry requirements and physical verification signoff criteria.
• Support advanced technology node designs, preferably 5nm and/or 3nm.

4. Engineering Change Orders (ECO)

• Implement logical ECOs using Synopsys Formality ECO.
• Perform timing ECOs and timing optimization using PrimeClosure.
• Debug and resolve timing, connectivity, and physical design issues.
• Collaborate with RTL, synthesis, DFT, STA, and physical verification teams to achieve design closure.

Required Technical Skills

• 6 9 years of experience in VLSI Physical Design.
• Strong hands-on experience with Synopsys Fusion Compiler.
• Expertise in RTL-to-GDSII implementation and physical design flow.
• Experience with floorplanning, placement, CTS, routing, and timing closure.
• Hands-on experience with PrimeTime, StarRC, RedHawk-SC, and Calibre.
• Experience with Formality ECO and PrimeClosure.
• Strong understanding of STA, setup/hold analysis, PPA optimization, DRC, LVS, antenna, and density checks.
• Experience with advanced process nodes such as 5nm and 3nm is preferred.
• Strong debugging, problem-solving, and communication skills.

Preferred Qualifications

• Experience in block-level and full-chip/SoC physical implementation.
• Knowledge of low-power design techniques and physical design optimization.
• Experience with signoff closure and tape-out activities.
• Ability to work independently in a distributed engineering team.

Candidate Requirements

• Experience: 6 9 years
• Availability: Immediate joiners to candidates with a maximum 15-day notice period
• Work Location: Remote / USA-wide opportunities
• Domain: VLSI / Semiconductor / ASIC Physical Design

Interested candidates: Please share your updated resume highlighting relevant physical design tools, technology nodes, project experience, current location, work authorization, and availability.

Job Tags

Full time, Contract work, Immediate start, Remote work

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